CD4010BE CD4010B CD4010 CMOS Hex Non-Inverting Kuwit | Ubuy

The CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement. Parallel clocking provides synchronous control and hence faster response from all counting outputs. ) @ CL = 50 pF and VDD–VSS = 10 V, Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C Preset Enable and individual Jam inputs provided, Binary or decade up/down counting, 5-V, 10-V, and 15-V parametric ratings BCD outputs in decade mode, 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of ’B’ Series CMOS Devices